Demand for bandwidth has increased. Accordingly, ICs have increasingly more transceivers to meet such increasing demand for bandwidth. Such transceivers may have associated therewith one or more phase-locked loops (“PLLs”). Furthermore, such ICs may include one or more clock modules, and such clock modules may each include a PLL. Conventionally, such clock modules have been used to provide a system clock signal separate from clocking of such transceivers. In the past, transceiver PLLs were not used to provide system clock signals for any of several reasons. For example, because a transceiver may be interrupted during a reset thereof, a transceiver clock signal could not be used as a system clock signal for lack of continuity or stability. Furthermore, for a programmable logic device, an array of programmable resources (“programmable fabric”) had to have a same data width as a transceiver data width as only one frequency could be produced for such transceiver clock signal. Lastly, in applications where a transceiver buffer between a Physical Coding Sublayer block (“PCS”) and a Physical Medium Attachment Sublayer block (“PMA”) is bypassed, a transmitter phase interpolator (“PI”) may rotate preventing use of a clock output from such PI from being used as a system clock signal.
Hence, it would be desirable to provide an IC that overcomes one or more of the above limitations in order to provide a more robust ability to use a transceiver PLL to provide a system clock signal to reduce the number of clock modules on such an IC.